The present invention relates to a technology on so-called upstream design for systems including large-scale integrated circuits (LSIs).
Complementary metal-oxide semiconductor (CMOS) LSIs, which were first commercialized three decades ago and have made up the majority of the market for more than a decade, now face a decisive turning point. LSI manufacturers have hitherto shaped strategies on LSIs by only concentrating on scale-down of LSIs. However, at last, it has become difficult to attain both higher speed and lower power of CMOS LSIs simultaneously by only achieving scale-down thereof (see “From scale-down to all-around ability; Reshaping of CMOS strategy”, Nikkei Microdevices, August 2000, pp. 118-121).
One of problems causing difficulty in attaining both higher speed and lower power simultaneously is a leak current.
More specifically, as a gate oxide film is made thinner with the advance in scale-down of an LSI, a gate leak current increases so greatly that requirements of an application apparatus fail to be satisfied. For example, in the generation of devices having a gate oxide film as thin as 2 to 2.5 nm conforming to the 0.15 ìm rule, the tunnel current allowed to flow through the gate oxide film exceeds a standby current value of the order of several ìA required for a mobile apparatus. If it is attempted to suppress the standby current to conform to the requirements of the application apparatus, further thinning of the gate oxide film, which is essential for attaining higher speed, will no more be obtained. This indicates that attainment of both higher speed and lower power simultaneously becomes very difficult.